Options flow for semiconductor stocks: reading the chip sector tape

Semiconductor subsector flow map

The semiconductor sector is internally diverse, each subsector responds to different demand cycles and catalysts:

The bellwether chain: NVDA as sector anchor

Since 2023, NVIDIA has become the single most important options flow signal in the semiconductor sector, and arguably in all of tech. The bellwether chain works as follows:

1. NVDA pre-earnings positioning: In the two to three weeks before NVDA earnings, institutional traders build call positions that reflect expectations about data center revenue and forward guidance. This pre-earnings call accumulation in NVDA is often the strongest signal in the entire sector for any given quarter.
2. NVDA print → sector repricing: When NVDA reports, the implied guidance revisions cascade through AMD (GPU competition), AVGO/MRVL (AI networking silicon), MU (HBM memory for AI training), and AMAT/LRCX (fab equipment for expanded AI silicon production). Flow in these names accelerates within hours of an NVDA print.
3. Second-order plays: Institutional traders who can't get clean NVDA exposure (the options are expensive) often use AMD, MRVL, or MU as leveraged proxies with better premium-to-expected-move ratios. Monitoring flow in these names for unusual activity that appears disconnected from their own fundamentals often signals a NVDA readthrough play.

Premium thresholds for meaningful NVDA signals are necessarily high given its market cap, a $500K sweep in NVDA is relatively routine; look for $2M+ prints as genuinely institutional-scale signals. AMD has a lower threshold given its smaller float: $200K+ sweeps are notable.

AI and HPC positioning signals

The AI infrastructure buildout has created sustained call flow patterns across the semiconductor sector that are distinct from traditional chip cycle positioning:

• Hyperscaler capex announcements: When Amazon, Google, Microsoft, or Meta announce increased data center capex (typically during their own earnings calls), call sweeps across NVDA, AVGO, MU, and MRVL follow within hours. Institutional traders who monitor hyperscaler commentary position immediately in AI semiconductor calls. This is one of the cleanest and most reliable readthrough patterns in the sector.
• HBM memory tightness signals in MU: High-bandwidth memory (HBM) is a critical component for AI training chips. When supply signals suggest HBM is tightening (lead time extensions, allocation conversations), MU options flow skews aggressively bullish, call sweeps at elevated Vol/OI in the 30–60 DTE range. This often precedes MU's own guidance revisions.
• Custom silicon displacement risk: As hyperscalers (Amazon's Trainium, Google's TPU, Microsoft's Maia) build custom AI chips to reduce NVDA dependence, put flow in NVDA can reflect institutional concern about market share erosion. Distinguishing this from standard earnings hedging requires looking at DTE (custom silicon risk is typically expressed in longer-dated puts, 90–180 DTE).
• Inference vs training positioning: The market has begun distinguishing between AI training (NVDA dominant) and inference (AMD, Qualcomm, and custom silicon competitive). Flow patterns that show AMD calls outperforming NVDA calls over multiple sessions may reflect a rotation from training to inference exposure.

Memory and PC cycle signals

Micron (MU) options flow is a window into the DRAM and NAND memory cycles that affect a broad range of technology end markets:

• DRAM ASP cycle signals: Memory pricing moves in well-established supply/demand cycles. When DRAM ASPs are rising (under-supply), MU call sweeps accelerate; when oversupply hits, put accumulation builds, often months before the price data appears in official reports. Institutional traders with alternative data on memory pricing (spot DRAM prices, contract pricing trends) express their read through MU options.
• PC cycle leading indicators: PC shipment data from IDC and Gartner gives a quarterly read on consumer and commercial PC demand, which directly affects DRAM demand. Options flow in Intel and Qualcomm (both heavily PC-exposed) tends to move in advance of these reports when institutional traders have early read on PC sell-through data.
• HBM as a cycle breakout: The HBM premium in AI hardware spending has partially decoupled MU from the traditional consumer DRAM cycle. Flow that shows MU calls building while the PC cycle remains weak signals institutional positioning on HBM-driven revenue rather than traditional memory volume.

Chip equipment as a leading indicator

Chip equipment stocks (AMAT, LRCX, KLAC, ASML) are some of the best leading indicators for semiconductor sector health, and their options flow provides early signals:

• WFE (wafer fab equipment) spending cycle: When foundries and chipmakers are expanding capacity, equipment orders surge 12–18 months before revenue flows through to chip companies. AMAT and LRCX options call sweeps often precede formal WFE guidance upgrades by weeks, institutional traders monitoring equipment booking data position ahead of consensus estimate revisions.
• KLAC inspection equipment as a quality signal: KLA Corporation provides process control and yield monitoring equipment, its orders are a leading indicator for how aggressively fabs are trying to improve leading-node yield. Call flow in KLAC ahead of equipment surveys often precedes positive fab yield data that boosts chip company margins.
• ASML as the EUV capacity bottleneck indicator: ASML's extreme ultraviolet lithography machines are the bottleneck for leading-node (<3nm) chip production. ASML order data and delivery schedules directly affect NVDA and AMD supply capacity timelines. Options flow in ASML (listed on Nasdaq as ADR) is less liquid than US-listed names, but unusual prints carry significant macro signal for the leading-edge chip capacity outlook.

SMH ETF options signals

SMH (VanEck Semiconductor ETF) is the primary institutional vehicle for sector-level semiconductor positioning:

SOXX (iShares Semiconductor ETF) is the alternative with slightly different composition, it equal-weights more toward Intel and Texas Instruments. Comparing SMH vs SOXX flow can reveal whether institutional positioning is AI-focused (would show up more in SMH given NVDA's heavy weight) or broader chip cycle (more balanced in SOXX).

Export controls and geopolitical risk flow

The semiconductor sector is uniquely exposed to geopolitical risk, US export controls on advanced chips and equipment have become a recurring catalyst for options flow:

• BIS export control announcements: The Bureau of Industry and Security periodically updates restrictions on chip exports to China. These announcements generate immediate put buying across NVDA (H100/H800 export restrictions), AMAT, LRCX (equipment restrictions), and broader sector ETFs. The put flow before formal announcements sometimes reflects institutional awareness of the regulatory pipeline through Washington monitoring services.
• TSMC Taiwan risk premium: TSM ADR options activity spikes during escalations in Taiwan Strait tensions. Institutional traders hedge TSMC exposure through SMH puts or direct TSM put purchases, the flow pattern during geopolitical flare-ups is predictable and informative about how seriously the market is pricing invasion risk at any given moment.
• CHIPS Act beneficiary positioning: Companies receiving CHIPS Act grants (Intel, TSMC US fab, Micron fab expansions) see localized call flow around award announcements and construction milestones. This is a distinct pattern from the cycle positioning flow, it's policy-driven and often shows up in longer DTE (60–180 days).

Semiconductor catalyst calendar

Foundry vs fabless: how the manufacturing model drives different flow patterns

The foundry/fabless split is the most consequential structural divide in semiconductors for options traders. Fabless designers, NVDA, AMD, QCOM, AVGO, MRVL, own no manufacturing capacity. They create chip designs, then pay pure-play foundries like TSMC, Samsung Foundry, and GlobalFoundries to manufacture wafers on their behalf. This asset-light model gives fabless companies high gross margins (often 50–65%) and eliminates the multi-billion dollar capex burden of running a fab, but it also means they live and die by foundry allocation, lead times, and wafer pricing.

Pure-play foundries operate on the opposite economics: massive fixed capital investment (a leading-edge 3nm fab costs $20 billion or more to build), high sensitivity to utilization rates, and significant pricing power when capacity is tight. TSMC's utilization data, disclosed quarterly, functions as a real-time health check for the entire fabless ecosystem. When TSMC reports utilization above 90%, it signals that demand from NVDA, AMD, Apple, and others is running ahead of capacity, creating pricing power and ASP expansion for the fabless names. When utilization falls into the low-70% range, it means foundry capacity is abundant, competition on wafer pricing intensifies, and ASP pressure follows for fabless chip companies.

The most reliable leading indicator for US fabless company earnings is TSMC's monthly revenue report, released on the 10th of each following month. Because TSMC recognizes revenue when wafers ship, not when the fabless company ultimately ships product to customers, TSMC revenue leads US fabless earnings by approximately 6–8 weeks. A string of accelerating monthly TSMC revenue prints is a call signal for NVDA, AMD, QCOM, and AVGO; decelerating TSMC revenue is an early put signal before fabless earnings confirm the miss. Options traders who monitor TSMC monthly data and cross-reference it against current fabless call/put ratios have a structural information advantage over analysts waiting for quarterly earnings.

GlobalFoundries (GFS) and OSAT (outsourced semiconductor assembly and test) companies, ASX, AMAT service revenues, Amkor Technology, fill out the downstream manufacturing picture. GFS specializes in mature-node (28nm and above) chips for automotive, industrial, and RF applications. Its utilization rates are a leading indicator for the automotive and IoT semiconductor cycle, which is distinct from the leading-edge AI cycle. When GFS utilization is recovering and ASX OSAT volumes are growing, the analog/automotive semi recovery is underway, a call signal for NXPI, ON, TXN, and ADI before their own quarterly results confirm it.

• TSMC monthly revenue (10th of month): The most time-sensitive foundry data point; accelerating prints lead fabless earnings by 6–8 weeks and are a reliable sector-wide call setup signal.
• TSMC utilization rate (quarterly): Above 90% signals foundry capacity tightness and ASP expansion for fabless names; below 75% signals oversupply and margin pressure.
• ASP (average selling price) cycle: When foundry demand exceeds capacity, fabless companies gain pricing power, call flow builds; when capacity is abundant, ASP compression is a put signal across fabless names.
• GlobalFoundries utilization: Leading indicator for the mature-node (automotive/industrial) cycle, distinct from the leading-edge AI cycle tracked through TSMC.
• OSAT volumes (Amkor, ASX): Assembly and test volumes confirm wafer demand is flowing through to finished chips, validating the upstream foundry revenue signal as genuine end-demand rather than inventory build.
• Fabless gross margin trajectory: In tight foundry markets, fabless gross margins expand (call signal); in loose markets, margin compression typically appears in guidance before revenue misses, watch for gross margin guidance cuts as the first put signal.

Automotive and industrial semiconductor demand: the longest lead-time segment

Automotive semiconductors represent the most structurally stable, and most timing-intensive, segment of the chip sector for options traders. The design-in cycle for automotive chips runs 3–5 years from initial design selection to vehicle production. Once a chip is designed into a vehicle platform, it ships for 5–7 years regardless of broader economic conditions, because OEMs cannot easily substitute components mid-platform without recertifying the entire system. This creates a radically different demand profile than AI/data center chips, where upgrade cycles run 12–18 months.

The primary automotive semiconductor names, NXP Semiconductors (NXPI), ON Semiconductor (ON), STMicroelectronics (STM), and Texas Instruments in its automotive-heavy revenue segments, exhibit flow patterns that respond to vehicle production data and OEM procurement signals rather than the hyperscaler capex commentary that drives NVDA and AMD. The key tracking mechanism is SAAR (seasonally adjusted annual rate) for US auto production, combined with global vehicle production data from IHS Markit and JATO. When global vehicle production is above 90 million units annualized and trending upward, automotive semi demand is structurally healthy. The flow signal appears when production data diverges from expectations, either accelerating ahead of consensus (call flow in NXPI, ON) or decelerating below trend (put flow).

EV adoption is creating a structural step-change in semiconductor content per vehicle that is independent of the traditional IC volume cycle. A conventional internal combustion engine vehicle contains 50–60 semiconductor devices. A full EV platform (battery management system, motor control, onboard charger, ADAS) contains 150–200 discrete semiconductors plus significant SoC content. As EV penetration rises, tracked monthly through EV delivery data from Tesla, BYD, GM, and Ford, the automotive semiconductor revenue per vehicle grows even when total vehicle unit volumes are flat. This structural content growth is a multi-year call thesis for the automotive semi names and generates LEAPS call accumulation (6–18 month expirations) whenever EV adoption data beats expectations.

Industrial semiconductor demand, tracked through Texas Instruments (TI), Analog Devices (ADI), and Microchip Technology (MCHP), follows the ISM Manufacturing PMI with a 2–3 month lag. This lag is predictable: when PMI rises above 50 and sustains for 3+ consecutive months, industrial customers begin releasing purchase orders for semiconductors they had been deferring during the contraction. Call flow in TI and ADI typically begins building 4–6 weeks into a sustained PMI expansion, well before analysts revise earnings estimates upward. The put setup is symmetric: PMI falling below 50 and holding there for 2+ months signals industrial semi order deferral, and put accumulation builds in TI and MCHP as institutional traders position ahead of guidance cuts.

• SAAR (seasonally adjusted annual rate): Monthly US auto production rate; above-trend readings drive call flow in NXPI, ON, and automotive-heavy TXN segments.
• EV delivery data (Tesla, BYD, GM, Ford, monthly): Each percentage point of EV penetration growth adds disproportionate semiconductor content per vehicle, a structural call driver for automotive semi names.
• Design-win announcements: When an OEM confirms chip selection for a new vehicle platform, it creates 5–7 years of revenue visibility, LEAPS call accumulation in the winning supplier follows within days of the announcement.
• Book-to-bill ratio (NXPI, ON, quarterly): Above 1.0 signals more orders than shipments (inventory restocking cycle beginning); below 1.0 signals customer drawdown (inventory digestion, put signal).
• ISM Manufacturing PMI: Sustained above-50 readings lead industrial semi call flow by 4–6 weeks; sustained below-50 readings lead put flow in TI, ADI, MCHP on the same lag.
• Automotive inventory correction timing: The 2021–22 chip shortage caused OEMs to over-order; when automotive customers began disclosing "inventory digestion," it marked the put flow entry point for a multi-quarter correction in ON and NXPI.

Power semiconductors and the EV/energy transition: silicon carbide and the next chip supercycle

Power semiconductors, devices that control, convert, and regulate electrical power, are the fastest-growing chip category in the sector, driven by two compounding structural tailwinds: EV adoption and renewable energy buildout. Unlike logic chips (where Moore's Law drives performance) or memory (where density drives cost), power semiconductors compete on efficiency (how little energy is wasted as heat during power conversion) and voltage/current handling capability. The shift from silicon-based power devices to silicon carbide (SiC) represents the most significant materials transition in power semiconductors in 30 years.

Silicon carbide enables EV powertrains to convert battery power to motor torque approximately 5–8% more efficiently than conventional silicon-based inverters. In a market where EV range anxiety is a primary adoption barrier, that efficiency gain is a genuine competitive differentiator that OEMs will pay a significant premium for. SiC power chips are currently 3–4 times more expensive per unit than equivalent silicon devices, but the performance advantage justifies the price premium for EV OEMs targeting range leadership. This creates substantial revenue-per-vehicle growth for SiC suppliers even without unit volume expansion.

The key SiC players and their flow dynamics differ significantly by their position in the supply chain. ON Semiconductor has committed significant capital to SiC manufacturing, with capacity expansion programs tied to multi-year OEM supply agreements. STMicroelectronics has pursued SiC vertical integration, manufacturing its own SiC substrates rather than sourcing from external suppliers, creating margin expansion optionality that the market prices into STM options when OEM design-win announcements validate the strategy. Wolfspeed (WOLF) is the pure-play SiC substrate supplier: it built significant substrate capacity in 2022–23 in anticipation of demand that materialized more slowly than projected, creating a multi-quarter put flow environment until utilization rates recover. Infineon Technologies, the European SiC leader, is less liquid in US options but meaningful for cross-checking the global SiC demand signal.

The second demand vector for power semiconductors, independent of the EV cycle, is utility-scale energy storage and solar power inverters. Both require power devices for DC-to-AC conversion, and both are growing driven by renewable energy buildout policy and falling solar/battery costs. EIA (Energy Information Administration) monthly data on renewable energy capacity additions is the most reliable leading indicator for this segment. When EIA data shows renewable installation rates accelerating above trend, power semi call flow appears in ON and STM within 4–6 weeks as institutional traders position ahead of demand confirmation.

• SiC design-win announcements: When an OEM confirms SiC chip selection for a new EV platform, the winning SiC supplier gains multi-year revenue visibility, LEAPS call accumulation (9–18 month expirations) follows the announcement.
• EV production volumes (monthly, Tesla, BYD, GM, Ford): Direct translation to SiC wafer demand; each EV produced consumes 30–50 SiC power devices in the powertrain alone.
• Wolfspeed (WOLF) utilization rate: The leading indicator for SiC substrate market balance; recovery from the 2023–24 capacity overhang shows up in utilization improvement before revenue confirms.
• EIA renewable capacity addition data (monthly): Acceleration in solar and storage installations drives solar inverter power chip demand, a second call vector for ON and STM independent of the EV cycle.
• SiC vs silicon ASP premium: When OEM qualification programs confirm SiC adoption at scale, the price premium sustains, if OEMs begin substituting back to silicon on cost pressure, it is a margin compression put signal for SiC-heavy suppliers.
• Industrial UPS and data center power: Data center power density growth (driven by AI GPU cluster power consumption) is creating demand for high-voltage power devices in UPS systems and PDUs, an AI-adjacent call driver for power semi names that is often overlooked in the GPU-focused flow narrative.

Networking semiconductor cycle: how hyperscaler capex drives MRVL, AVGO, and CIEN flow

Data center networking chips are distinct from compute chips, they handle the physical movement of data between GPU servers, storage arrays, and the external internet. As AI training clusters have scaled from hundreds to tens of thousands of GPUs, the demand for higher-speed interconnects has grown faster than compute demand itself. A modern AI training cluster requires that every GPU communicate with every other GPU at multi-terabit speeds; the networking silicon enabling that communication has become as strategically important as the GPUs themselves. This structural shift has made networking semiconductor options one of the most active and informative flow segments in the entire tech sector.

Marvell Technology's custom ASIC business is the clearest example of how networking chip strategy translates into options flow. Marvell designs custom networking and compute chips specifically for Amazon (the Graviton CPU series and Trainium AI inference chip), Microsoft (Cobalt CPUs), and Google. These custom ASIC engagements are multi-year programs worth hundreds of millions of dollars in annualized revenue, and when they are announced or expanded, they create sustained LEAPS call accumulation in MRVL, typically 9–18 month expirations, because the revenue visibility is genuinely long-dated. The critical insight for flow reading: MRVL custom ASIC revenue ramps slowly (chip design to volume production is typically 18–24 months), so institutional traders who understand the program timeline buy long-dated calls well before revenue appears in reported numbers.

Broadcom's networking portfolio, the Tomahawk and Trident switch chip families that run the majority of the world's hyperscale data center switching fabric, is the leading indicator for data center switching upgrade cycles. When hyperscalers announce network capacity expansions or spine-leaf architecture upgrades, AVGO networking segment revenue accelerates. The challenge for flow reading is that AVGO's overall options activity is complicated by its VMware acquisition, which added significant enterprise software revenue. Traders must parse AVGO earnings call commentary carefully to distinguish between networking capex-driven beats (bullish for the sector-wide AI infrastructure read) and VMware revenue ramp beats (company-specific, less sector-informative).

The 800G and 1.6T optical interconnect upgrade cycle has created a distinct flow opportunity in optical networking companies. As AI training clusters grow and GPU-to-GPU data rates must increase, the optical transceivers connecting servers and switches must upgrade from 400G to 800G and eventually 1.6T. Ciena (CIEN), Viavi Solutions (VIAV), and II-VI (now Coherent, COHR) are the primary beneficiaries. CIEN options flow is the most liquid proxy for this upgrade cycle: call accumulation in CIEN with 60–120 DTE typically appears 4–8 weeks before hyperscaler network spending commentary appears in earnings calls, suggesting institutional traders are tracking optical transceiver shipment data directly from supply chain sources.

• Hyperscaler capex commentary (Amazon, Microsoft, Google, Meta earnings calls): References to "network capacity expansion," "co-location upgrades," or "spine-leaf refresh" are the clearest verbal triggers for networking semi call flow, positions follow within 2–4 weeks.
• MRVL custom ASIC announcement: Design-win disclosures from Marvell for hyperscaler custom silicon are multi-year revenue events, LEAPS call accumulation (9–18 month expirations) is the institutional response pattern.
• AVGO networking segment revenue (quarterly): Strip out VMware software contribution to isolate the pure networking chip revenue signal, acceleration here is bullish for the broader AI infrastructure call thesis.
• CIEN optical transceiver shipment data: CIEN quarterly revenue is the most liquid proxy for the 800G/1.6T optical upgrade cycle; call accumulation in CIEN 4–8 weeks before earnings has historically preceded beats driven by hyperscaler optical capex.
• InfiniBand vs Ethernet competition: NVDA's InfiniBand (via Mellanox) competes with Ethernet for AI cluster interconnect; when hyperscaler announcements favor open Ethernet standards, it is a call signal for MRVL and AVGO and a relative put signal for NVDA's networking segment.
• Co-location and DCI (data center interconnect) spending: Long-haul optical network investment between data centers accelerates alongside AI cluster buildout, a secondary call driver for CIEN and COHR that is independent of the within-cluster networking cycle.

Semiconductor inventory cycles: how the build-burn pattern creates predictable call and put sequences

The semiconductor inventory cycle is the most reliable pattern in the entire sector for generating options flow signals months ahead of earnings confirmation. The cycle is structurally predictable because chip manufacturing physics create inescapable supply-demand mismatches: fabs require 12–24 months to design, build, and qualify new capacity, which means supply cannot respond quickly to demand changes. When demand rises faster than supply, customers over-order to secure allocation, inflating order books and signaling false demand strength. When supply eventually catches up (or demand softens), the over-ordering reverses into sharp inventory digestion that surprises every analyst who was extrapolating the over-order book as real end-demand. This cycle has repeated every 3–5 years for four decades, and sophisticated options traders have learned to position in it before earnings catalysts confirm the turn.

There are three primary data sources for tracking cycle position in real time. First, company-reported inventory days (days inventory outstanding, or DIO), disclosed in quarterly earnings: when DIO rises above 120 days across the sector, inventory correction is building and put accumulation is the institutional response; when DIO falls below 70 days, the correction is near its end and call flow builds in anticipation of recovery. Second, the book-to-bill ratio from the Semiconductor Industry Association (SIA), published monthly: above 1.0 means orders are exceeding shipments (demand is accelerating relative to supply, call signal); below 1.0 means shipments exceed new orders (inventory digestion, put signal). Third, SEMI equipment orders: fab equipment is ordered 12–18 months before the capacity it creates comes online, making equipment orders a long-lead indicator of future supply. Accelerating equipment orders signal coming oversupply 12–18 months forward, a put signal for the terminal point of the current shortage cycle.

The cycle sequence plays out with enough regularity that institutional traders treat it as a framework for options positioning across the sector. Phase 1 (shortage): demand exceeds supply, pricing power builds, call flow accumulates across the sector. Phase 2 (over-ordering): customers double-order to secure allocation, order books inflate, analysts extrapolate the inflated demand, call positioning peaks. Phase 3 (correction): end-demand softens while supply catches up to over-inflated orders; customers cancel orders and draw down inventory rather than placing new orders; earnings guidance cuts cascade across the sector; put flow builds. Phase 4 (digestion): DIO is elevated, book-to-bill is below 1.0, but the rate of guidance cuts is slowing, put flow peaks, call flow begins rebuilding in names closest to the cycle bottom. Phase 5 (recovery): DIO normalizes, book-to-bill crosses above 1.0, equipment orders accelerate, call flow builds across the sector 6–8 weeks before revenue confirms recovery.

SMH options open interest functions as the most liquid sector-wide inventory cycle indicator. When SMH put open interest reaches historical extremes (measured as a multiple of its 52-week average) and then begins declining, put holders reducing positions rather than adding, it signals that the cycle bottom is close. This put OI peak-and-decline pattern has historically appeared 4–8 weeks before the earnings quarter that marks the actual revenue trough, giving options traders a timing edge over analysts waiting for confirmed fundamental improvement.

• Days inventory outstanding (DIO), sector average: Above 120 days = correction building (put signal); below 70 days = recovery approaching (call signal); monitor MU, AMAT, TXN, and NXPI as the most revealing reporters.
• SIA book-to-bill ratio (monthly): The most timely sector-wide order-to-shipment balance indicator; above 1.0 for 3+ consecutive months is a durable call setup; below 1.0 for 3+ months is a durable put setup.
• SEMI equipment orders (monthly): A 12–18 month leading indicator for future supply; accelerating equipment orders today signal potential oversupply in 12–18 months, giving a long-dated put setup signal even during current shortages.
• SMH put open interest extremes: When SMH put OI peaks and begins declining, the cycle is turning, historically 4–8 weeks ahead of confirmed revenue trough in quarterly earnings.
• Phase 4 (digestion) call accumulation targets: MU and AMAT are typically the first-recovery names, MU because memory pricing turns before chip volumes, AMAT because new fab commitments begin before capacity comes online.
• Analyst estimate revision lag: Sell-side analysts systematically lag the inventory cycle by 1–2 quarters because they wait for confirmed data; this lag creates the options pricing inefficiency that cycle-aware traders exploit, buying calls in late Phase 4 when analyst estimates are still being cut.

Case studies: three semiconductor options flow sequences from supply-demand signal to outcome

The following case studies illustrate how the signal frameworks above translated into specific options flow sequences and outcomes. Each begins with a trackable real-world catalyst, describes the flow pattern that emerged, and quantifies the result for traders who positioned early. These are historical examples intended to illustrate how the frameworks function, not performance guarantees for future trades.